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as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 1 rev. 1. 0 june 2 013 128 m x 8 bit ddr ii synchronous dram (sdram) confidential advanced (rev . 1. 0 , jun . / 20 1 3 ) features ? jedec standard compliant ? ? power supplies: v dd & v ddq = +1.8 v ? 0.1v ? operating temperature range - commercial (0 ~ 85c) - industrial ( - 40 ~ 95c) ? f ully synchronous operation ? ? ? ? ? ? ? ? ? ? write latency = read latency - 1 t ck ? b urst lengths: 4 or 8 ? burst type: sequential / interleave ? dll enable/disable ? on - die termination (odt) ? rohs compliant ? ? 7.8 s @ 0 Q tc Q +85 3.9 s @ +85 tc Q + 9 5 ? 60 - ball 8 x 1 0 x 1.2mm ( max) fbga p ackage - pb and halogen free overview the ddr2 sdram is a high - speed cmos double - data - rate - two (ddr 2) , synchronous dynamic random - access memory (sdram) containing 1024 mbits in a 8 - bit wide data i / os . it is internally configured as a 8 - bank dram , 8 banks x 16 mb addresses x 8 i/os . the de vice is designed to comply with ddr2 dram key features such as posted cas # with additive latency, w rite latency = r ead latency - 1 and on die termination (odt) . all of the control and address inputs are synchronized with a pair of externally supplied differ ential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck # falling) all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs # ) in a source synchronous fashion. the address bus is used to convey row, co lumn, and bank address information in ras #, cas # multiplexing style. accesses begin with the registration of a bank activate command , and then it is followed by a read or write command. read and write accesses to the ddr2 sdram are 4 or 8 - bit burst orient ed; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of the burst sequence. a sequential and gapless data rate is possible depending on burst length, cas latency , and speed grade of t he device . table 1. ordering information par t number clock frequency data rate po w er supply package as4c 128 m 8 d2 - 25bcn 400mhz 800mbps/pin v dd 1 .8v , v dd q 1.8v fbga as4c 128 m 8 d2 - 25bi n 400mhz 800mbps/pin v dd 1.8v , v ddq 1.8v fbga b: indicate s 60 - ball 8 x 10 x 1.2mm (max) fbga package c: indicates commercial temperature i: indicates industrial temperature n: indicates pb and halogen free rohs tabl e 2. speed grade information spee d grade clock frequency cas latency t rcd (ns) t rp (ns) ddr2 - 800 400 mhz 5 12.5 12.5
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 2 rev. 1. 0 june 2 013 figure 1. ball assignment (fbga top view) a b c d e 1 2 3 7 8 9 v d d r d q s # v s s v s s q d q s # v d d q f d q 6 v s s q d m / r d q s d q s v s s q d q 7 g v d d q d q 1 v d d q v d d q d q 0 v d d q h d q 4 v s s q d q 3 d q 2 v s s q d q 5 j v d d l v r e f v s s v s s d l c k v d d k c k e w e # r a s # c k # o d t l b a 2 b a 0 b a 1 c a s # c s # a 1 0 a 1 a 2 a 0 v d d v s s a 3 a 5 a 6 a 4 a 7 a 9 a 1 1 a 8 v s s v d d a 1 2 n c n c a 1 3
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 3 rev. 1. 0 june 2 013 figure 2 . block diagram c k # c k e c s # r a s # c a s # w e # d l l c l o c k b u f f e r c o m m a n d d e c o d e r c o l u m n c o u n t e r a d d r e s s b u f f e r a 1 0 / a p a 0 ~ a 9 a 1 1 ~ a 1 3 b a 0 ~ b a 2 c k d q s d q s # r d q s r d q s # d q b u f f e r d m d q 7 d q 0 ~ o d t 1 6 m x 8 c e l l a r r a y ( b a n k # 0 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 1 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 2 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 3 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 4 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 5 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 6 ) r o w d e c o d e r c o l u m n d e c o d e r 1 6 m x 8 c e l l a r r a y ( b a n k # 7 ) r o w d e c o d e r c o l u m n d e c o d e r c o n t r o l s i g n a l g e n e r a t o r r e f r e s h c o u n t e r d a t a s t r o b e b u f f e r m o d e r e g i s t e r
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 4 rev. 1. 0 june 2 013 figure 3. state diagram ( e ) m r s s e t t i n g m r , e m r ( 1 ) e m r ( 2 ) e m r ( 3 ) o c d c a l i b r a t i o n i n i t i a l i z a t i o n s e q u e n c e i d l e a l l b a n k s p r e c h a r g e d s e l f r e f r e s h i n g r e f r e s h i n g p r e c h a r g e p o w e r d o w n a c t i v a t i n g a c t i v e p o w e r d o w n b a n k a c t i v e w r i t i n g w r i t i n g w i t h a u t o p r e c h a r g e p r e c h a r g i n g r e a d i n g w i t h a u t o p r e c h a r g e r e a d i n g a c t c k e l c k e h c k e l w r r d a r d a w r a w r a w r r d r d p r , p r a p r , p r a p r , p r a r d a w r a c k e l c k e h c k e l s r f c k e h r e f c k e l w r r d p r c k e l c k e l a u t o m a t i c s e q u e n c e c a m m a n d s e q u e n c e c k e l = c k e l o w , e n t e r p o w e r d o w n c k e h = c k e h i g h , e x i t p o w e r d o w n , e x i t s e l f r e f r e s h a c t = a c t i v a t e w r ( a ) = w r i t e ( w i t h a u t o p r e c h a r g e ) r d ( a ) = r e a d ( w i t h a u t o p r e c h a r g e ) p r ( a ) = p r e c h a r g e ( a l l ) ( e ) m r s = ( e x t e n d e d ) m o d e r e g i s t e r s e t s r f = e n t e r s e l f r e f r e s h r e f = r e f r e s h n o t e : u s e c a u t i o n w i t h t h i s d i a g r a m . i t i s i n d e n t e d t o p r o v i d e a f l o o r p l a n o f t h e p o s s i b l e s t a t e t r a n s i t i o n s a n d t h e c o m m a n d s t o c o n t r o l t h e m , n o t a l l d e t a i l s . i n p a r t i c u l a r s i t u a t i o n s i n v o l v i n g m o r e t h a n o n e b a n k , e n a b l i n g / d i s a b l i n g o n - d i e t e r m i n a t i o n , p o w e r d o w n e n t r y / e x i t , t i m i n g r e s t r i c t i o n s d u r i n g s t a t e t r a n s i t i o n s , a m o n g o t h e r t h i n g s , a r e n o t c a p t u r e d i n f u l l d e t a i l .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 5 rev. 1. 0 june 2 013 ball descriptions table 3 . ball descripti ons symbol type description ck, ck # input differential clock: ck, ck # are driven by the system clock. all sdram input signals are sampled on the crossing of po sitive edge of ck and negative edge of ck #. output ( r ead) data is referenced to the crossings of ck and ck # ( both directions of crossing). cke input clock enable: cke activates ( high) and deactivates ( low ) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and bu rst address is froze n as long as the cke remains low . when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. b a 0 - b a 2 input bank address : b a 0 - b a 2 define to which bank the bankactivate, read , write, or bankprecharge command is being applied. a0 - a1 3 input address inputs: a0 - a1 3 are sampled during the bankactivate command (row address a0 - a1 3 ) and read/write command (column address a0 - a 9 with a10 defining auto precharge ). a13 row address use on x8 components only. cs # input chip select: cs # enables (sampled low) and disables (sampled high) the command decoder . all commands are masked when cs # is sampled high. cs # provides for external bank selection on systems with multiple banks. it is conside red part of the command code. ras # input row address strobe: the ras # signal defines the operation co mmands in conjunction with the cas # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # and cs # are asserted "low" and cas # is asserted "high," either the bankactivate command or the precha rge command is selected by the we # signal. when the we # is asserted "high," the bankactivate command is selected and the bank designated by b a is turned on to the act ive state. when the we # is asserted "low," the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. cas # input column address strobe: the cas # signal defines the operation commands in con junction with the ras # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # is held "high" and cs # is asserted "low," the column access is started by asserting cas # "low." then, the read or write co mman d is selected by asserting we # high " or low ". we # input write enable: the we # signal defines the operation commands in conjunction with the ras # and cas # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . the we # i nput is used to select the bankactivate or precharge command and read or write command. dqs, dqs # r dqs r dqs # input / output bidirectional data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. fo r the rdqs option using dm pin can be enabled via the emr(1) to simplify read timing. the data strobes dqs and rdqs may be used in single ended mode or paired with the optional complementary signals dq s# and rdqs# to provide differential pair signaling to t he system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 6 rev. 1. 0 june 2 013 dm input data input mask: input data is masked when dm is sampled high during a write cycle. x8 device, the function of dm or rdqs/r qds # is enabled by emrs command. dq0 C dq 7 input / output data i/o: bi - directional data bus. odt input on die termination: odt enables internal termination resistance. it is applied to each dq, dqs / dqs # , r dqs / r dqs # and dm signal. the odt pin is ignored i f the emr ( 1) is programmed to disable odt. v dd supply power supply: + 1.8 v ? 0.1v v ss supply ground v dd l supply dll power supply: + 1.8 v ? 0.1v v ss d l supply dll ground v ddq supply dq power: + 1.8 v ? 0.1v . v ssq supply dq ground v ref supply reference volta ge for inputs: +0.5*v ddq nc - no connect: these pins should be left unconnected.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 7 rev. 1. 0 june 2 013 operation mode table 4 shows the truth table for the operation commands. table 4 . truth table (note (1), (2 )) command state cke n - 1 cke n dm b a 0 - 2 a 10 a 0 - 9, 11 - 13 cs # ras # cas # we # bankactivate idle (3) h h x v row address l l h h single bank precharge any h h x v l x l l h l all banks precharge any h h x x h x l l h l write active (3) h h x v l column address (a0 C a9) l h l l wr ite with autoprecharge active (3) h h x v h l h l l read active (3) h h x v l column address (a0 C a9) l h l h read and autoprecharge active (3) h h x v h l h l h ( extended ) mode register set idle h h x v op code l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x refresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x l h h h power down mode entry idle h l x x x x h x x x l h h h power down mode exit any l h x x x x h x x x l h h h data in put mask disable active h x l x x x x x x x data input mask enable(5) active h x h x x x x x x x note 1: v=valid data, x=don't care, l=low level, h =high level note 2: cke n signal is input level when commands are provided. note 3 : cken - 1 signal is input level one clock cycle before the commands are provided. note 4: these are states of bank designated by b a signal. note 5: device state is 4 , and 8 bur st operation. note 6: ldm and udm can be enable d respectively.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 8 rev. 1. 0 june 2 013 functional description read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a progr ammed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 - ba 2 select the bank; a0 - a 13 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. prior to normal ope ration, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. ? power - up and initialization ddr2 sdrams must be powered up an d initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*v ddq and odt *1 at a low state (all other inputs may be undefined. ) the v dd voltage ramp time must be no greater than 200ms from when v dd ramps from 300mv to v dd min; and during the v dd voltage ramp, |v dd - v ddq | Q 0.3 v - v dd , v ddl and v ddq are driven from a single power converter output, and - v tt is limited to 0.95 v max, and - v ref tracks v ddq /2. or - apply v dd before or at the same time as v ddl . - apply v ddl before or at the same time as v ddq . - apply v ddq be fore or at the same time as v tt & v ref . at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. f or the minimum of 200 s after stable power and clock ( ck, ck # ), then apply nop or deselect and take cke high . 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs ( 2) command, provide l ow to ba0 and ba2 , h igh to ba1.) 6. issue emrs ( 3) command. (to issue emrs ( 3) comm and, provide l ow to ba2, h igh to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "d ll enable" command, provide "l ow " to a0, "h igh " to ba0 and "l ow " to ba1 and ba2 .) 8. issue a mode register set command for dll reset. (to issue dll reset command, provide "h igh " to a8 and "l ow " to ba0 - ba2 ) 9. issue precharge all command. 10. issue 2 or more auto - refresh commands. 11. issue a mode regis ter set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resett ing the dll. ) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment) .if ocd calibration is not used, emrs ocd default command (a9=a8= a7= high ) followed by emrs ocd c alibration mo de exit command (a9=a8=a7= low ) mu st be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. note 1: to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 9 rev. 1. 0 june 2 013 ? mode register set(mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, wr, and various vendor specific options to make ddr2 sdram useful for various applications.the default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0 and ba1, while controlling the state of address pins a0 - a1 3 . the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the mode register.the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode re gister contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state.the mode register is divided into various fields depending on functionality. - burst length field (a2, a1, a0) : this field specifies the data length of column access and selects the burst length. - addressing mode select field (a3) : the addressing mode can be interleave mode or sequential mode. both sequential mode and interleave mode support burst leng th of 4 and 8. - cas latency field (a6, a5, a4) : this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. (tcac(min) Q cas latency x t ck ) - test mode field (a7); dll reset mode field (a8) : these two bits must be programmed to "00" in normal operation. - write recovery field (a11, a10, a9) : the wr register is used by the ddr2 sdram during write with auto precharge opera tion. the wr register is used by the ddr2 sdram during write with auto precharge operation. - active power down field (a12) : pd mode enables the user to determine the active power - down mode, which determines performance versus power savings. oes not apply to precharge pd mode. - (ba0 - ba1): bank addresses to define mrs selection . table 5. mode register bitmap b a 2 ba1 b a0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 * 2 0 0 0 * 2 pd wr dll tm cas latency bt burst length mo de register a8 dll reset a7 mode a3 burst type a2 a1 a0 bl 0 no 0 normal 0 sequential 0 1 0 4 1 yes 1 test 1 interleave 0 1 1 8 n ote 1 : for ddr2 - 800, wr min is determined by t ck (avg) max and wr max is determined by t ck (avg) min. wr [cycles] = ru {t wr [ ns]/t ck (avg)[ns]}, where ru stands for round up. the mode register must be programmed to this value.this is also used with t rp to determine t dal . n ote 2: ba2 and a13 are reserved for future use and must be set to 0 when programming the mr. a12 active power down exit time write recovery for autoprecharge *1 0 fast exit (use t xard ) a11 a10 a9 wr(cycles) a6 a5 a4 cas latency 1 slow exit (use t xards ) 0 0 0 reserved 0 0 0 reserved 0 0 1 2 0 0 1 reserved ba1 ba0 mrs mode 0 1 0 3 0 1 0 reserved 0 0 mr 0 1 1 4 0 1 1 3 0 1 emr(1) 1 0 0 5 1 0 0 4 1 0 emr(2) 1 0 1 6 1 0 1 5 1 1 emr(3) 1 1 0 reserved 1 1 0 6 1 1 1 reserved 1 1 1 reserved
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 10 rev. 1. 0 june 2 013 ? e x tended mode register set (emrs ) - emr(1) the extended mode register(1) stores the data for enabling or disabling the dll, output driver strength, odt value selection and additive latency. the default value of the extended mode register is not defined, therefore the ext ended mode register must be written after power - up for proper operation. the extended mode register is written by asserting low on cs # , ras # , cas # , we # , ba1 and high on ba0, while controlling the states of address pins a0 ~ a1 3 . the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register. mode register contents can be chang ed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data - output driver. a3~a5 determine the additive l atency, a2 and a6 are used for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disable and a11 is used for rdqs enable. - dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initi alization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re - enabled upon exit of self refresh operation. any time the dll is enabled (and su bsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck pa rameters. table 6 . extended mode register emr ( 1) bitmap b a2 ba1 b a0 a1 3 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 * 3 0 1 0 * 3 qoff rdqs dqs# ocd program rtt additive latency rtt d.i.c dll extended mode register ba1 ba0 mrs mode a6 a2 rtt (nominal) 0 0 mr 0 0 odt disable a0 dll enable 0 1 emr(1) 0 1 75 a9 a8 a7 ocd calibration program a1 output driver impedance control 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 reserved 0 full strength 0 1 0 reserved 1 reduced strength 1 0 0 reserved 1 1 1 ocd calibration default * 1 a5 a4 a3 additive latency 0 0 0 0 a12 qoff * 2 0 0 1 1 0 output buffer enabled 0 1 0 2 a10 dqs# 1 output buffer disabled 0 1 1 3 0 enable 1 0 0 4 1 disable a1 1 rdqs enable * 4 1 0 1 5 0 disable 1 1 0 6 1 enable 1 1 1 reserved note 1 : after setting to default, ocd c alibration mode needs to be exited by setting a9 - a7 to 000.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 11 rev. 1. 0 june 2 013 note 2 : output disabled C dqs, dqss, dqss# , rdqs, rdqs# . this feature is intended to be use d during i dd characterization of read current. n ote 3 : a13 and ba2 are reserved for future use and must be set to 0 when programming the mr. n ote 4 : if rdqs is enabled, the dm function is disabled. rdqs is active for reads and do not care for writes. table 7 . extended mode register emr ( 1) bitmap a11 (rdqs enable) a10 (dqs# enable) rdqs /dm rdqs# dqs dqs# 0 (disable) 0 (enable) dm hi - z dqs dqs# 0 (disable) 1(disable) dm hi - z dqs hi - z 1(enable) 0 (enable) rdqs rdqs# dqs dqs# 1(enable) 1(disable) rdqs hi - z dqs hi - z - emr(2) the extended mode register (2) controls refresh related features. the default value o f the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power - up for proper operation. the extended mode register(2) is written by asserting low on cs # , ras # , cas # , we # , high on ba1 and low on ba0, wh ile controlling the st a tes of address pins a0 ~ a1 3 . the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register (2). the mode register set command cycle time (t mrd ) must be satisfied to complete th e write operation to the extended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. table 8 . extended mode register emr(2) bitmap b a2 ba1 b a0 a1 3 a1 2 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *3 1 0 0 *1 srf 0 *1 extended mode register(2) a7 high temperature self - refresh rate enable 0 disable 1 enable *2 note 1 : the rest bits in emrs(2) are reserved for future use and all bits in emrs(2) except a7, ba0 and ba1 must be programmed to 0 when setting the extended mode register(2) during initialization. note 2: due to the migration natur e , user needs to ensure the dr am part supports higher than 8 5 tcase temperature self - refresh entry. if the high temperature self - refresh mode is supported then controller can set the emrs2[a7] bit to enable the self - refresh rate in case of higher than 8 5 temperature self - refresh oper ation. n ote 3 : ba2 is reserved for future use and must be set to 0 when programming the mr.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 12 rev. 1. 0 june 2 013 - emr(3) no function is defined in extended mode register(3).the default value of the extended mode register(3) is not defined, therefore the extended mode regi ster(3) must be programmed during initialization for proper operation. table 9 . extended mode register emr ( 3) bitmap b a2 ba1 b a0 a1 3 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 1 0 *1 extended mode register(3) not e 1: all bits in emr ( 3) except ba0 and ba1 are reserved for future use and must be set to 0 when programming the emr ( 3).
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 13 rev. 1. 0 june 2 013 ? odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance for ea ch dq, dqs/ dqs # , r dqs/ r dqs # , d m signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. t he odt function is support ed for active and standby modes . it is turned off and not supported in self refresh mode. figure 4 . functional representation of odt table 10 . odt dc electrical characteristics paramete r/condition symbol min . nom . max . unit note rtt effective impedance value for emrs(a6,a2)=0,1; 75 rtt1(eff) 60 75 90 1 rtt effective impedance value for emrs(a6,a2)=1,0;150 rtt2(eff) 120 150 180 1 rtt effective impedance value for emrs(a6,a2)=1,1;50 rtt3(eff) 40 50 60 1 rtt mismatch tolerance between any pull - up/pull - down pair rtt(mis) - 6 - 6 % 2 n ote 1: measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin seperately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. note 2: measurement defintion for rtt (mis): measure volta ge (vm) at test pin (midpoint) with no load . s w 1 r v a l 1 v d d q s w 1 r v a l 1 v s s q s w 3 r v a l 3 v d d q s w 3 r v a l 3 v s s q s w 2 r v a l 2 v d d q s w 2 r v a l 2 v s s q i n p u t p i n d r a m i n p u t b u f f e r s w i t c h ( s w 1 , s w 2 , s w 3 ) i s e n a b l e d b y o d t p i n . s e l e c t i o n a m o n g s w 1 , s w 2 , a n d s w 3 i s d e t e r m i n e d b y r t t ( n o m i n a l ) i n e m r . t e r m i n a t i o n i n c l u d e d o n a l l d q s , d m , d q s , d q s # , r d q s a n d r d q s # p i n s ( ) ( ) ? ih il ih il v ac v ac rtt(eff)= i(v (ac))-i(v (ac)) 1 100% ?? ?? ?? ?? ddq 2xvm rtt(mis)= v
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 14 rev. 1. 0 june 2 013 ? bank activate command the bank activate command is issued by holding cas # and we # high with cs # and ras # low at the rising edge of the cl ock. the bank addresses ba0 - ba 2 are used to select the desired bank. the row addresses a0 through a1 3 are used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto - precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd min specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive latencies of 0, 1, 2, 3, and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined (t rc ). the minimum time inte rval between bank active commands is t rrd in order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. there are two rules. one for restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follows: - 8 bank device sequential bank activation restriction : no more than 4 banks may be activated in a rolling t faw window. converting to clocks is done by dividing t faw [ns] by t ck [ns] or t ck [ns], depending on the speed bin, and rounding up to next integer value. as an example of the rolling window, if ru{ (t faw / t ck ) } or ru{ (t faw / t ck ) } is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. - 8 bank device precharge all allowance : t rp for a precharge all command for an 8 bank de vice will equal to t rp + 1 x t ck or t rp + 1 x t ck , depe nding on the speed bin, where t rp = ru{ t rp / t ck } and t rp is the value for a single bank precharge. ? read and write access modes after a bank has been activated, a r ead or w rite cycle can be executed . this is accomplished by setting ras # high , cs # and cas # low at the clocks rising edge. we # must also be defined at this time to determine whether the access cycle is a r ead operation (we # high ) or a w rite operation (we # low ). the ddr2 sdram provides a f ast column access operation. a single read or write command will initiate a serial r ead or w rite operation on successive clock cycles. the boundary of the burst cycle is strictly restricted to specific segments of the page length. any system or application incorporating random access memory products should be properly designed, tested, and qualified to ensure proper use or access of such memory products. disproportionate, excessive, and/or repeated access to a particular address or addresses may result in r eduction of product life. ? post ed cas# posted cas # operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas# r ead or w rite command to be issued immediately after the ras bank activate command (or any time during the ras # - cas # - delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the ca s latency (cl). therefore if a user chooses to issue a r/w command before the t rcd min, then al (greater than 0) must be written into the emr(1). the write latency (wl) is always defined as rl - 1 ( r ead l atency - 1) where r ead l atency is defined as the sum o f additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) ? burst mode operation burst mode operation is used to provid e a constant flow of data to memory locations ( w rite cycle), or from memory locations ( r ead cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. fo r 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either seq uential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst r ead or w rite operations are supported. interruption of a burst r ead or w rite operation is prohibited, when burst length = 4 is programmed. for burst i nterruption of a r ead or w rite burst when
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 15 rev. 1. 0 june 2 013 burst length = 8 is used, see the burst interruption section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. table 1 1 . burst definition, addressing sequence of sequential and inte rleave mode burst length start address sequential interleave a2 a1 a0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 ? burst read command the burst read command is initiated by having cs # and cas # low while holding ras # and we # high at the rising edge of th e clock. the address inputs determine the starting column address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equ al to the value of the r ead l atency (rl). the data s trobe output (dqs ) is driven low 1 clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data - out appears on the dq pin in phase with the dqs signal in a sou rce synchronous manner. the rl is equal to an additive latency (al) plus cas l atency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the al is defined by the extended mode register set (1 ) (emrs ( 1)). ddr 2 sdram pin timings are specified for eithe r single ended mode or differen tial mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin tim ings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs an d its complement, dqs # . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 10 k resis tor to insure proper operation. ? burst write operation the burst write command is initiated by having cs # , cas # and we # low while holding ras # high at the rising edge of the clock. the address inputs determine the starting column address. writ e la tency (wl) is defined by a r ead latency (rl) minus one and is equal to (al + cl - 1);and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe sig nal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for each positiv e dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, wh ich is 4 or 8 bit burst. when t he burst has finished, any additional data supp lied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time fr om the completion of the burst w rite to bank precharge is the w rite recovery time (wr). ddr2 sdram pin timings are specified for either si ngle ended mode or differential mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at the specified ac/dc levels. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 16 rev. 1. 0 june 2 013 its complement, dqs # . t his distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 10k resistor to insure prop er operation.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 17 rev. 1. 0 june 2 013 ? write data mask one w rite data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on w rite operations as the data bits, and though used i n a uni - directional manner, is internally loaded identically to data bits to insure mat ched system timing. dm is not used during read cycles. ? precharge operation the precharge c ommand is used to precharge or close a bank that has been activated. the prec harge command is triggered when cs # , ras # and we # are low and cas # is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba2, ba1, and ba0 are us ed to define which bank to precharge when the command is issued. table 1 2 . bank selection for precharge by address bits a10 ba2 ba1 ba0 precharged bank(s) low low low low bank 0 only low low low high bank 1 only low low high low bank 2 only low low hig h high bank 3 only low high low low bank 4 only low high low high bank 5 only low high high low bank 6 only low high high high bank 7 only high don t care don t care don t care all banks ? burst read operation followed by precharge minimum read to pre charge command spacing to the same bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which additive latency (al) + bl/2 clocks after a read command. a new bank active ( command) may be issued to the same bank after the ras# precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initi ates the last 4 - bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time from al + 2 clocks aft er the read to the precharge command. ? burst write operation followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not s upport any burst interrupt by a precharge command. t wr is an analog timing parameter and is not the programmed value for t wr in the mrs.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 18 rev. 1. 0 june 2 013 ? auto precharge operation before a new row in an active bank can be opened, the active bank must be precharged u sing either the precharge command or the auto - precharge function. when a read or a write command is given to the ddr2 sdram, the cas # timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the ear liest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high wh en the read or write command is issued, then the auto - precharge function is engaged. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is cas latency (cl) c lock cycles before the end of the read burst. auto - precharge also be implemented during write commands. the precharge operation engaged by the auto precharge command will not begin until the last data of the burst write sequence is properly stored in the m emory array. this feature allows the precharge operation to be partially or completely hidden during burst r ead cycles (dependent upon cas latency) thus improving system performance for random data access. the ras # lockout circuit internally delays the pre charge operation until the array restore operation has been completed (t ras satisfied) so that the auto precharge command may be issued with any r ead or w rite command. ? burst read with auto precharge if a10 is high when a read command is issued, the read with auto - precharge function is engaged. the ddr2 sdram starts an auto - precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, th e start point of auto - precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of auto - precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is p ushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto - precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto - precharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks a fter the last 4 - bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras # precharge time (t rp ) has been satisfied from the clock at which the auto - precharge begins. (2) the ras # cycle time (t rc ) from the previous bank activation has been satisfied. ? burst write with auto precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins prech arge operation after the completion of the burst write plus w rite recovery time ( t wr ). the bank undergoing auto - precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) the data - in to bank activ ate delay time (wr + t rp ) has been satisfied. (2) the ras # cycle time (t rc ) from the previous bank activation has been satisfied.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 19 rev. 1. 0 june 2 013 table 1 3 . precharge & auto precharge clariification from command to command minimum delay between from command to to comma nd unit note read precharge (to same bank as read) al+bl/2+max(rtp,2) - 2 t ck 1,2 precharge all al+bl/2+max(rtp,2) - 2 read w/ap precharge (to same bank as read w/ap) al+bl/2+max(rtp,2) - 2 t ck 1,2 precharge all al+bl/2+max(rtp,2) - 2 write precharge ( to same bank as write) wl+bl/2+ t wr t ck 2 precharge all wl+bl/2+ t wr write w/ap precharge (to same bank as write w/ap) wl+bl/2+ t wr t ck 2 precharge all wl+bl/2+ t wr precharge precharge (to same bank as precharge) 1 t ck 2 precharge all 1 precharg e all precharge 1 t ck 2 precharge all 1 n ote 1: rtp [ cycles ] =ru {t rtp [ ns]/ t ck ( avg ) [ ns]}, where ru stands for round up. note 2: for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank.the prechrage period is satisfied after t rp or t rp all( =t rp for 8 bank device + 1x t ck ) depending on the latest precharge command issued to that bank. ? refresh command when cs # , ras # and cas # are held low and we # high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the refresh command (ref) can be applied. an address counter, internal to the de vice, supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the ddr2 sdram will be in the precharged (idle) state. a delay betw een the refresh command (ref) and the next activate command or subsequent refresh command must be greater than or equal to the refresh cycle time (t rfc ).to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the abs olute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 * t refi . ? self refresh operation the sel f refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is defined by having cs # , ras # , cas # and cke # held low with we # high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs c ommand. once the command is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode all of the external signals except cke, are dont care. for proper self refresh operation all power supply pins (v dd , v ddq , v ddl and v ref ) must be at valid levels. the dram initiates a minimum of one refresh command internally within t ck e pe riod once it enters self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock mu st be stable prior to cke going back high. once self refresh exit is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the enti re self refresh exit period t xsrd for proper operation except for self refresh re - entry. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command(refresh period o f t rfc ). nop or d eselect commands must be registered on each positive clock edge during the self refresh exit interval t xsnr . odt
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 20 rev. 1. 0 june 2 013 should be turned off during t xsrd . the use of self refresh mode introduces the possibility that an internally timed refresh ev ent can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. ? p ower - down power - down is synchronously ente red when cke is registered low along with nop or deselect command. no read or write operation may be in progress when cke goes low . these operations are any of the following: read burst or write burst and recovery. cke is allowed to go low while any of oth er operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exit ing power - down mode for proper read operation. if power - down occurs when all banks are precharged, this mode is referred to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. for active power - down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as standard active power - down mode and a fast power - down exit timing defined by the t xard tim ing parameter can be used. when a12 is set to high this mode is referred as a power saving low power active power - down mode. this mode takes longer to exit from the power - down mode and the t xards timing parameter has to be satisfied. entering power - dow n deactivates the input and output buffers, excluding ck, ck # , odt and cke. also the dll is disabled upon entering precharge power - down or slow exit active power - down, but the dll is kept enabled during fast exit active power - down. in power - down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are dont care. power - down duration is limited by 9 times t refi of the device. the power - down state is synchronously exited when cke is register ed high (along with a nop or deselect command). a valid, executable command can be applied with power - down exit latency, t xp , t xard or t xards , after cke goes high . power - down exit latencies are defined in the ac spec table of this data sheet. ? asynchronous cke low event dram requires cke to be maintained high for all valid operations as defined in this datasheet. if cke asynchronously drops low during any valid peration dram is not guaranteed to preserve the contents of array. if this event occurs, memo ry controller must satisfy dram timing specification tdelay efore turning off the clocks. stable clocks must exist at the input of dram before cke is raised high again. dram must be fully re - initialized. dram is ready for normal operation after the initi alization sequence. ? input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock fr equency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depen ding on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc. during dll re - lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ? no operation c ommand the no operation command should be used in cases when the ddr2 sdram is in an idle or a wait state. the purpose of the no operation command (nop) is to prevent the ddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs # is low with ras # , cas # , and we # held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. ? deselect command the des elect command performs the same function as a no operation command. deselect command occurs when cs # is brought high at the rising edge of the clock, the ras # , cas # , and we # signals become dont cares.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 21 rev. 1. 0 june 2 013 table 1 4 . absolute maximum dc rating s symbol para meter rating unit note v dd voltage on v dd pin relative to vss - 1.0 ~ 2.3 v 1,3 v ddq voltage on v ddq pin relative to vss - 0.5 ~ 2.3 v 1,3 v dd l voltage on v dd l pin relative to vss - 0.5 ~ 2.3 v 1,3 v in , v out voltage on any p in relative to vss - 0. 5 ~ 2.3 v 1 , 4 t stg storage t emperature - 55~1 0 0 c 1 ,2 n ote1 : stress greater than those listed under absolute maximum ratings may cause permanent damage to the devices. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note2: storage temperature is the case tem perature on the center/top side of the dram. note3: when v dd and v ddq and v ddl are less than 500mv, vref may be equal to or less than 300mv. note 4 : voltage on any input or i/o may not exceed voltage on v ddq . t able 1 5 . operating temperature condition symb ol parameter rating unit note t op e r operating t emperature commercial 0~ 85 c 1, 2 industrial - 4 0~ 95 c 1, 2 n ote 1: operating temperature is the case surface temperature on center/top of the dram. n ote 2 : whe n t oper excee ds 85 , it is requ ired to set 3.9us trefi in auto refresh mode or to set 1 for emrs(2) bit a7 in self refresh mode. table 1 6 . recommended dc operating conditions (sstl_1.8) symbol parameter min. typ. max. unit note v dd power s upply v oltage 1.7 1.8 1.9 v 1 v dd l power s upply v oltage f or dll 1.7 1.8 1.9 v 5 v ddq power s upply v oltage for i/o buffer 1.7 1.8 1.9 v 1,5 v ref input r eference v oltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq m v 2,3 v tt termination v oltage v ref - 0.04 v ref v ref + 0.04 v 4 note 1 : th ere is no specific device vdd supply voltage requirement for sstl_1 8 compliance. however under all conditions v ddq must be less than or equal to v dd. note 2 : the value of v ref may be selected by the user to provide optimum noise margin in the system. typica lly the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . note 3 : peak to peak ac noise on v ref may not exceed 2 % v ref (dc). note 4 : v tt of transmitting device must track v ref of r eceiving device. note 5 : v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v ddl tied together
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 22 rev. 1. 0 june 2 013 table 1 7 . input logic level ( v dd = 1.8 v ? op e r = - 4 0~ 9 5 ? symbol parameter - 25 unit min. max. v ih ( d c ) dc input logic high voltage v ref + 0. 125 v ddq + 0. 3 v v il ( d c ) dc input low voltage - 0.3 v ref - 0. 125 v v ih ( ac ) ac input high voltage v ref + 0. 2 v ddq +v peak v v il ( ac ) ac input low voltage v ss q C v peak v ref C 0. 2 v v id ( a c) ac different ial voltage 0 .5 v ddq + 0. 6 v v i x ( a c) ac differential crosspoint voltage 0.5 x v ddq - 0.175 0.5 x v ddq +0.175 v n ote 1: refer to ove rshoot/undershoot specification for v peak value: maximum peak amplitude allowed for overshoot and undershoot . table 1 8 . ac input test co nditions ( v dd = 1.8 v ? oper = - 4 0~ 9 5 ? symbol parameter - 25 unit note v ref input reference voltage 0.5 x v ddq v 1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew rate input signal minimum slew rate 1.0 v /ns 2, 3 note1 : input waveform timing is referenced to the input signal crossing through the v ih / il ( ac ) level applied to the device under test. note2 : the input signal minimum slew rate is to be maintained over the range from v ref to v ih ( ac ) min for rising edges and the rang e from v ref to v il ( ac ) max for falling edges . note3 : ac timings are referenced with input waveforms switching from v il ( ac ) to v ih ( ac ) on the positive transitions and v ih ( ac ) to v il ( ac ) on the negative transitions. table 1 9 . differential ac output p arameters ( v dd = 1.8 v ? oper = - 4 0~ 9 5 ? symbol parameter - 25 unit note min. max. v ox(ac ) ac differential cross point voltage 0.5x v ddq - 0.125 0.5x v ddq +0.125 v 1 note 1 : the typical value of v ox ( ac ) is expected to be about 0.5 x v ddq of the tr ansmitting device and v ox ( ac ) is expected to track variations in v ddq . v ox ( ac ) indicates the voltage at which differential output signals must cross. table 20 . ac overshoot/undershoot specification for address and control pins (a0 - a12, ba0 - ba 2 , cs#, ra s#, cas#, we#, cke, odt) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0. 5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.66 v - ns maximum undershoot area below v ss 0.66 v - ns
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 23 rev. 1. 0 june 2 013 table 2 1 . ac overshoot/undershoot specification for clock, data, strobe, and mask pins (dq, dqs, dqs#, dm, ck, ck#) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maxim um overshoot area above v dd 0.23 v - ns maximum undershoot area below v ss 0.23 v - ns table 2 2 . output ac test conditions ( v dd = 1.8 v ? oper = - 4 0~ 9 5 ? symbol parameter - 25 unit note v otr output timing measurement reference level 0.5xv ddq v 1 no te 1 : the v ddq of the device under test is referenced. table 2 3 . output dc current drive ( v dd = 1.8 v ? oper = - 4 0~ 9 5 ? symbol parameter - 25 unit note i oh ( dc ) output minimum source dc current - 13.4 ma 1, 3, 4 i ol ( dc ) output minimum sink dc curre nt 13.4 ma 2, 3, 4 note1 : v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq ) /i oh must be less than 21 for values of v out between v ddq and v ddq - 280 mv. note2 : v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 for values of v out between 0 v and 280 mv. note3 : the dc value of v ref applied to the receiving device is set to v tt note4 : the values of i oh ( dc ) and i ol ( dc ) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and vil max minus a noise margin are delivered to an sstl_18 receiver. the actual curre nt values are derived by shifting the desired driver operating point (see jedec standard : section 3.3 of jesd8 - 15a ) along a 21 load line to define a convenient driver current for measurement. table 2 4 . capacitance (v dd = 1 . 8 v, f = 1mhz, t op e r = 25 ? symbol parameter d dr2 - 800 unit min. max . delta c in input capacitance : command and address 1 .0 1.75 0.25 pf c ck input cap acitance (ck, ck#) 1 .0 2.0 0.25 pf c i/o dm , dq, dqs input/output capacitance 2 .5 3.5 0.5 pf n ote : these parameters are periodically sampled and are not 100% tested.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 24 rev. 1. 0 june 2 013 table 2 5 . idd specification parameters and test conditions ( v dd = 1.8 v ? oper = - 4 0~ 9 5 ? t ck =t ck ( min ), t rc = t rc ( min ), t ras = t ras ( min ); cke is high, cs # is high between valid commands; address bus inputs are switching ; d ata bus inputs are switching i dd0 70 ma operating one bank active - read - precharge current: i out = 0ma; bl = 4, cl = cl ( min ), al = 0; t ck = t ck ( min ),t rc = t rc ( min ), t ras = t ras ( min ), t rcd = t rcd ( min );cke is high, cs # is high between valid commands;addr ess bus inputs are switching; data pattern is same as i dd4w i dd1 85 ma precharge power - down current: all banks idle;t ck =t ck ( min ); cke is low; other control and address bus inputs are stable ; data bus inputs are floating i dd2p 10 ma precharge quiet sta ndby current: all banks idle; t ck =t ck ( min ); cke is high, cs # is high; other control and address bus inputs are stable ; data bus inputs are floating i dd2q 35 ma precharge standby current: all banks idle; t ck = t ck ( min ); cke is high, cs # is high; other control and address bus inputs are switching ; data bus inputs are switching i dd2n 40 ma active power - down current: all banks open; t ck =t ck ( min ); cke is low; other control and address bus inputs are stable ; data bus inputs are floating mrs (a12) =0 i dd3p 30 ma mrs (a12) =1 10 ma active standby current: all banks open; t ck = t ck ( min ), t ras = t ras ( max ), t rp = t rp ( min ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching ; data bus inputs are switching i dd3 n 50 ma operating burst write current: all banks open,continuous burst writes; bl = 4, cl = cl ( min ), al = 0; t ck = t ck ( min ), t ras = t ras ( max ), t rp = t rp ( min ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 120 ma operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl ( min ), al = 0; t ck = t ck ( min ), t ras = t ras ( max ), t rp = t rp ( min ); cke is high, cs # is high between valid commands; addre ss bus inputs are switching ; data bus inputs are switching i dd4r 120 ma burst refresh current: t ck = t ck ( min ); refresh command at every t rfc ( min ) interval; cke is high, cs # is high between valid commands; other control and address bus inputs are switch ing ; data bus inputs are switching i dd5 175 ma self refresh current: ck and ck # at 0v; cke 0.2v;other control and address bus inputs are floating ; data bus inputs are floating i dd6 9 ma operating bank interleave read current: all bank interleaving re ads, i out = 0ma; bl = 4, cl = cl ( min ), al =t rcd ( min ) - 1 x t ck ( min ); t ck = t ck ( min ), t rc = t rc ( min ), t rrd = t rrd ( min ), t rcd = t rcd ( min ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselect s .data pattern is s ame as idd4r i dd7 250 ma
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 25 rev. 1. 0 june 2 013 table 2 6 . electrical characteristics and recommended a.c. operating conditions (v dd = 1 . 8 v ? oper = - 4 0~ 9 5 ? t ck (avg) average clock period cl=4 - 8 n s 1 5 , 3 3 , 3 4 cl=5 2.5 8 n s cl=6 2.5 8 n s t ch (avg) average clock high pulse width 0.4 8 0.52 t ck 3 4 , 3 5 t cl (avg) average clock low pulse width 0.4 8 0.52 t ck 3 4 , 3 5 wl write command to dqs associated clock edge rl - 1 t ck t dqss dqs latching rising transitions to associated clock edges - 0.25 0.25 t ck 28 t dss dqs falling edge to ck setup time 0.2 - t ck 2 8 t ds h dqs falling edge hold time from ck 0.2 - t ck t dqsh dqs input high pulse width 0.35 - t ck t dqsl dqs input low pulse width 0.35 - t ck t wpre write pr eamble 0.35 - t ck t wpst write postamble 0.4 0.6 t ck 10 t is (base) address and control input setup time 0.175 - ns 5, 7, 9, 2 2, 27 t ih (base) address and control input hold time 0.25 - ns 5, 7, 9, 2 3, 27 t ipw control & address input pulse width for each input 0.6 - t ck t ds (base) dq & dm input setup time 0.05 - ns 6 - 8 , 20 , 2 6, 29 t dh (base) dq & dm input hold time 0.125 - ns 6 - 8 , 21 , 2 6, 29 t dipw dq and dm input pulse width for each input 0.35 - t ck t ac dq output access time from ck, ck# - 0.4 0.4 ns 38 t dqsck dqs output access time from ck, ck# - 0.35 0.35 ns 38 t hz data - out high - impedance time from ck, ck# - t ac (max) ns 1 8, 38 t lz(dqs) dqs(dqs#) low - impedance time from ck, ck# t ac (min) t ac (max) ns 1 8, 38 t lz(dq) dq low - impedance time from ck, ck# 2 t ac (min) t ac (max) ns 1 8, 38 t dqsq dqs - dq skew for dqs and associated dq signals - 0.2 ns 13 t hp ck half pulse width min (t ch ,t cl ) - ns 11, 12, 35 t qhs dq hold skew factor - 0.3 ns 12, 36 t qh dq/dqs output hold time from dqs t hp - t qhs - ns 37 t rpre re ad preamble 0.9 1.1 t ck 19, 39 t rpst read postamble 0.4 0.6 t ck 19, 40 t rrd active to active command period 7.5 - ns 4, 30 t faw four activate window 35 - ns 4, 30 t ccd cas# to cas# command delay 2 - t ck t w r write recovery time 15 - ns 30 t d al auto power write recovery + precharge time wr + t rp - ns 14, 31 t w tr internal write to read command delay 7.5 - ns 3, 24, 30 t rtp internal read to precharge command delay 7.5 - ns 3, 30 t cke cke minimum pulse width 3 - t ck 25
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 26 rev. 1. 0 june 2 013 t xs nr exit self refresh to no n - read command delay t rfc +10 - ns 30 t xs rd exit self refresh to a read command 200 - t ck t x p exit precharge power down to any command 2 - t ck t x ard exit active power down to read command 2 - t ck 1 t x ards exit active power down to read command(slow ex it, lower power) 8 - al - t ck 1, 2 t aond odt turn - on delay 2 2 t ck 16 t aon odt turn - on t ac (min) t ac (max) +0.7 ns 6, 16, 38 t aonpd odt turn - on (power - down mode) t ac (min) +2 2 t ck + t ac (max) +1 ns t aofd odt turn - off delay 2.5 2.5 t ck 17, 42 t aof odt turn - off t ac (min) t ac (max) +0.6 ns 17, 41 , 42 t aofpd odt turn - off (power - down mode) t ac (min) +2 2.5 t ck + t ac (max) +1 ns t anpd odt to power down entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck t mrd mode register set command cycle time 2 - t ck t mod mrs command to odt update delay 0 12 ns 30 t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck + t i h - ns 15 t rfc refresh to active/refresh command time 127.5 - ns 43 t refi average periodic refesh interval - 4 0 Q tc Q +85 - 7.8 s 43 +85 tc Q +9 5 - 3.9 s t rcd ras# to cas# delay time 12.5 - ns t rp row precharge delay time 12.5 - ns t rc row cycle delay time 57.5 - ns t ras row active delay time 45 70k ns
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 27 rev. 1. 0 june 2 013 general notes, which may apply f or all ac parameters: note 1: ddr2 sdram ac timing reference load the below figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical sys tem environment or a depiction of the actual load presented by a production tester. figure 5 . ac timing reference load the output timing reference voltage level for single ended signals is the crosspoint with vtt. the out put timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs # ) signal . note 2: slew rate measurement levels a) output slew rate for falling and rising edges is measured between v tt - 250 mv and v tt + 250 mv for single ended signals. for differential signals (e.g. dqs C dqs # ) output slew rate is measured between dqs C dqs # = - 500 mv and dqs C dqs # = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from v ref ( dc) to v ih ( ac) , min for rising edges and from v ref (dc) to v il (ac),max for falling edges.for d ifferential signals (e.g. ck C ck # ) slew rate for rising edges is measured f rom ck C ck # = - 250 mv to ck - ck # = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) v id is the magnitude of the difference between the input voltage on ck and the input voltage on ck # , or betweendqs and dqs # for differential strobe. note 3: ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as bellow v d d q d u t d q d q s d q s # r d q s r d q s # v t t = v d d q / 2 2 5 ? t i m i n g r e f e r e n c e p o i n t o u p u t
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 28 rev. 1. 0 june 2 013 figure 6 . slew rate test load note 4: differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differentia l mode depending on the s etting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationsh ips are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs # . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 10 k resistor to insure proper operation note 5: ac timings are for linear signal transitions. note 6: all voltages are referenced to v ss . note 7: these parameters guarantee device behavior, but they are not necessarily tested on each device.they may be guaranteed by devic e design or tester correlation note 8: tests for ac timing, i dd , and electrical (ac and dc) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage rang e specified. specific notes for dedicated ac parameters note 1: user can choose which active power down exit timing to use via mrs (bit 12). t xard is expected to be used for fast active power down exit timing. t xards is expected to be used for slow active power do wn exit timing where a lower power value is defined by each vendor data sheet. note 2: al=additive latency. note 3: this is a minimum requirement. minimum read to precharge timing is al+bl/2 provided that the t rtp and t ras (min) have been satisfied. note 4: a minimum of two clo cks (2* t ck ) is required irrespective of operating frequency. note 5: timings are specified with command/address input slew rate of 1.0 v/ns. note 6: timings are specified with dqs, dm, and dqs s ( dqs/rdqs in single ended mode) input slew rate of 1. 0v/ns. note 7: timings are sp ecified with ck/ck # differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode . note 8: data setup and hold time derating. for all input signals the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet . t ds(base) and t dh(base) value to the t ds and t dh derating value respectively. v d d q d u t d q d q s d q s # r d q s r d q s # v t t = v d d q / 2 2 5 ? t e s t p o i n t o u p u t
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 29 rev. 1. 0 june 2 013 example: t ds (total setup time) =t ds (base) + t ds .for slew rates in between the values listed in tables 28 , the derating values may obtained by linear interpolation.these values are typically not subject to pro duction test. they are verified by design and characterization. table 2 7 . ddr2 - 800 tds/tdh derating with differential data strobe note 9: t is and t ih (input setup and hold) derating for all input signals the total t is (setup time ) and t ih (hold time) required is calculated by adding the data sheet t is(base) and t ih(base) value to the t is and tih derating value respectively. example: t is (total setup time) = t is (base) + t is for slew rates in between the values listed in tables 2 9 , the derating values may obtained by linear interpolation.these values are typically not subject to production test. they are verified by design and characterization table 2 8 . derating values for ddr2 - 800 tis and tih derating values for d d r2 - 800 ck, ck # differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns tis tih tis tih tis tih units notes command/ address slew rate (v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 - 5 - 14 +25 +16 +55 +46 ps 1 0.8 - 13 - 31 +17 - 1 +47 +29 ps 1 0.7 - 22 - 54 +8 - 24 +38 +6 ps 1 0.6 - 34 - 83 - 4 - 53 +26 - 23 ps 1 0.5 - 60 - 125 - 30 - 95 0 - 65 ps 1 0.4 - 100 - 188 - 70 - 158 - 40 - 128 ps 1 0.3 - 168 - 292 - 138 - 262 - 108 - 232 ps 1 0.25 - 200 - 375 - 170 - 345 - 140 - 315 ps 1 0.2 - 325 - 500 - 295 - 470 - 265 - 440 ps 1 0.15 - 517 - 708 - 487 - 678 - 457 - 64 8 ps 1 0.1 - 1000 - 1125 - 970 - 1095 - 940 - 1065 ps 1 note 10: th e maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. note 11: min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). note 12: t qh = t hp C t qhs , where: tds, t dh derating values fo r d d 2 - 800 (all units in ps; the note applies to the entire table) dqs,dqs# differential slew rate 2.8 v/ns 2.4 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns td s tdh td s tdh td s tdh td s tdh td s tdh td s tdh td s tdh td s tdh td s tdh dq slew rate v/ns 2.0 100 63 100 63 100 63 - - - - - - - - - - - - 1.5 6 7 42 67 42 67 42 79 54 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - - 5 - 14 - 5 - 14 7 - 2 19 10 31 22 - - - - - - 0.8 - - - - - 13 - 31 - 1 - 19 11 - 7 23 5 35 17 - - - - 0.7 - - - - - - - 10 - 42 2 - 30 14 - 18 26 - 6 38 6 - - 0.6 - - - - - - - - - 10 - 59 2 - 47 14 - 35 26 - 23 38 - 11 0.5 - - - - - - - - - - - 24 - 89 - 12 - 77 0 - 65 12 - 53 0.4 - - - - - - - - - - - - - 52 - 140 - 40 - 128 - 28 - 116
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 30 rev. 1. 0 june 2 013 t hp = minimum half clock peri od for any given cycle and is defined by clock high or clock low (t ch , t cl ). t qhs accounts for: 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers. note 13: t dqsq : consists of data pin skew and output pattern effects, and p - channel to n - channel variati on of the output drivers as well as output slew rate mismatch between dqs / dqs # and associated dq in any given cycle. note 14: t dal = wr + ru{ t rp [ns] / t ck [ns] }, where ru stands for round up.wr refers to the t wr parameter stored in the mrs. for t rp , if the resul t of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. note 15: the clock frequency is allowed to change during self C refresh mode or precharge power - down mode. in case of clock frequency change during precharge power - down . note 16: odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently pe r speed bin. for ddr2 - 800, t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. note 17: odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bu s is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. f or ddr2 - 800 , if t ck (avg) = 2.5 ns is assumed, t aofd is 1.25 ns (= 0.5 x 2.5 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by c ounting the actual input clock edges. note 18: t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (t hz ), or begins driving (t lz ). note 19: t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). the actual voltage measuremen t points are not critical as long as the calculation is consistent. note 20: input waveform timing t ds with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint fo r a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs # signals must be monotonic between v il (dc)max and v ih (dc)min. note 21: input wavef orm timing t dh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the inpu t signal crossing at the v il (dc) level for a rising signal applied to the device under test. dqs, dqs # signals must be monotonic between v il (dc)max and v ih (dc)min. note 22: input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. note 23: input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under tes t. note 24: t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. note 25: t cke min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 c locks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 x t ck + t ih . note 26: if t ds or t dh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. note 27: these parameters are measured from a command/address signal (cke, cs # , ras # , cas # , we # , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck # ) crossing. the spec values are not affected by the amount of
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 31 rev. 1. 0 june 2 013 clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. note 28: these parameters are me asured f rom a data strobe signal ( dqs) crossing to its respective clock signal (ck/ck # ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as these are relative to the clock signal crossing. t hat is, these parameters should be met whether clock jitter is present or not. note 29: these parameters are measured from a data signal (dm , dq0 , dq1 , etc. ) transition edge to its respec tive data strobe signal ( dqs/ dqs# ) crossing. note 30: for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / t ck (avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. note 31: t dal [ t ck ] = wr [ t ck ] + trp [ t ck ] = wr + ru {t rp [ps] / t ck (avg) [ps] }, where wr is the value programmed in the mode register set. note 32: new units, t ck (avg) is introduced in ddr2 - 800. unit t ck (avg) represents the actual t ck (avg) of the input clock under operation. note 33: input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to ddr2 - 800. the jitter specified is a random jitter meeting a gaussian distribution. table 2 9 . input clock jitter spec pa rameter parameter symbol - 25 unit not e min . max . clock period jitter t jit ( per) - 100 100 p s 33 clock period jitter during dll locking period t jit (per,lck) - 80 80 p s 33 cycle to cycle clock period jitter t jit (cc) - 200 200 p s 33 cycle to cycle clock period jitter during dll locking pe riod t jit (cc,lck) - 160 160 p s 33 cumulative error across 2 cycles t err (2per) - 150 150 p s 33 cumulative error across 3 cycles t err (3per) - 175 175 p s 33 cumulative error across 4 cycles t err (4per) - 200 200 p s 33 cumulative error across 5 cycles t err ( 5per) - 200 200 p s 33 cumulative error across n cycles, n=6...10, inclusive t err (6 - 10per) - 300 300 p s 33 cumulative error across n cycles, n=11...50, inclusive t err (11 - 50per) - 450 450 p s 33 duty cycle jitter t jit (duty) - 100 100 p s 33 note 34: these parameter s are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min andmax of spec values are to be used for calculations in the table below.)
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 32 rev. 1. 0 june 2 013 table 30 . absolute clock period average values parameter symbol min . max . unit absolute clock period t ck (abs) t ck (avg),min + t jit (per),min t ck (avg),max + t jit (per),max ps absolute clock high pulse width t ch (abs) t ch (avg),min * t ck (avg),min + t jit (duty),min t ch (avg),max * t ck (avg),max + t jit (duty),max ps absolute clock low pulse width t cl (abs) t cl (avg),min * t ck (avg),min + t jit (duty),min t cl (avg), max * t ck (avg),max + t jit (duty), max ps note 35: t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for tqh calculation is determined by the following equation; t hp = min ( t ch (abs), t cl (abs) ), where, t ch (abs) is the minimum of the actual instantaneous clock high time; t cl (abs) is the minimum of the actual instantaneous clock low time; note 36: t qhs accounts for: 1) the pulse duration distortion of on - chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p - channel to n - channel variation of the output drivers note 37: t qh = t hp C t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half - pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} note 38: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err (6 - 10per) of the input clock. (outp ut deratings are relative to the sdram input clock.) note 39: when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) note 40: when the dev ice is operated with input clock jitter, this parameter needs to be derated by the actual t jit (duty) of the input clock. (output deratings are relative to the sdram input clock.) note 41: when the device is operated with input clock jitter, this parameter needs to be derated by { - t jit (duty),max - t err (6 - 10per),max } and { - t jit (duty),min - t err (6 - 10per),min } of the actual input clock. (output deratings are relative to the sdram input cl ock.) note 42: for t aofd of ddr2 - 800 , the 1/2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t ck (avg). t aof ,min and t aof ,max should each be derated by the same amount as the actual amount of t ch (avg) offset present at the dram input with respect to 0.5. note 43: if refresh timing is violated, data corruption may occur and the data must be re - writtern with valid data before a valid read can be executed.
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 33 rev. 1. 0 june 2 013 timing waveforms figure 7 . initia lization sequence after power - up figure 8 . odt update delay timing - tmod c k c k # t c h c k e c o m m a n d t c l t i s o d t t i s n o p p r e a l l e m r s m r s p r e a l l r e f r e f m r s e m r s e m r s a n y c m d 4 0 0 n s t r p t m r d t m r d t r p t m r d f o l l o w o c d f l o w c h a r t t o i t m i n 2 0 0 c y c l e d l l e n a b l e d l l r e s e t o c d d e f a u l t o c d c a l . m o d e e x i t n o t e 1 : t o g u a r a n t e e o d t o f f , v r e f m u s t b e v a l i d a n d a l o w l e v e l m u s t b e a p p l i e d t o t h e o d t p i n . t r f c t r f c e m r s c k u p d a t i n g r t t t i s n o p n o p n o p n o p n o p c m d t a o f d t m o d , m a x t m o d , m i n o l d s e t t i n g n e w s e t t i n g o d t n o t e 1 : t o p r e v e n t a n y i m p e d a n c e g l i t c h o n t h e c h a n n e l , t h e f o l l o w i n g c o n d i t i o n s m u s t b e m e t : - t a o f d m u s t b e m e t b e f o r e i s s u i n g t h e e m r s c o m m a n d . - o d t m u s t r e m a i n l o w f o r t h e e n t i r e d u r a t i o n o f t m o d w i n d o w , u n t i l t m o d , m a x i s m e t . t h e n t h e o d t i s r e a d y f o r n o r m a l o p e r a t i o n w i t h t h e n e w s e t t i n g , a n d t h e o d t s i g n a l m a y b e r a i s e d a g a i n t o t u r n e d o n t h e o d t . n o t e 2 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 3 : " s e t t i n g " i n t h i s d i a g r a m i s t h e r e g i s t e r a n d i / o s e t t i n g , n o t w h a t i s m e a s u r e d f r o m o u t s i d e . c k #
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 34 rev. 1. 0 june 2 013 figure 9 . odt update delay timing - t mod , as measured from outside c k # c k r t t t i s e m r s c m d t a o f d t m o d , m a x o l d s e t t i n g n e w s e t t i n g o d t n o p n o p n o p n o p n o p t a o n d n o t e 1 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 2 : " s e t t i n g " i n t h i s d i a g r a m i s m e a s u r e d f r o m o u t s i d e .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 35 rev. 1. 0 june 2 013 figure 1 0 . odt timin g for active standby mode figure 1 1 . odt timing for power - down mode c k # t 0 i n t e r n a l t e r m r e s . t i s t i s t a o n d c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f d t a o n , m i n t a o n , m a x t a o f , m i n t a o f , m a x r t t c k # t 0 i n t e r n a l t e r m r e s . t i s c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f p d , m a x t a o n p d , m i n r t t t a o f p d , m i n t a o n p d , m a x
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 36 rev. 1. 0 june 2 013 figure 1 2 . odt timing mode switch at entering power - down mode c k # c k t i s c k e t a o f d t a o n d o d t t a n p d t - 5 t - 4 t - 3 t - 2 t - 1 t 0 t 1 t 2 t 3 t 4 e n t e r i n g s l o w e x i t a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) t a o f p d m a x a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) r t t a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . r t t o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 37 rev. 1. 0 june 2 013 figure 1 3 . odt timing mo de switch at exit power - down mode figure 1 4 . bank activate command cycle (t rcd =3, al=2 , t rp =3 , t rrd =2 , t ccd =2) c k # c k t i s c k e t a o f d t a o n d o d t t a x p d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 e x i t i n g f r o m s l o w a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t i n t e r n a l t e r m r e s . t i s v i l ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . r t t t a o f p d m a x v i h ( a c ) r t t r t t r t t c k # t 0 t 1 t 2 t 3 t n t n + 1 t n + 2 i n t e r n a l r a s # - c a s # d e l a y ( > = t r c d m i n ) c a s # - c a s # d e l a y t i m e ( t c c d ) t r c d = 1 r e a d b e g i n s t n + 3 b a n k a r o w a d d r . b a n k a c o l . a d d r . b a n k b r o w a d d r . b a n k b c o l . a d d r b a n k a a d d r . b a n k b a d d r . b a n k a r o w a d d r . a d d i t i v e l a t e n c y d e l a y ( a l ) b a n k a a c t i v a t e b a n k a p o s t c a s # r e a d b a n k b a c t i v a t e b a n k b p o s t c a s # r e a d b a n k a p r e c h a r g e b a n k b p r e c h a r g e b a n k a a c t i v a t e r a s # - r a s # d e l a y t i m e ( > = t r r d ) b a n k a c t i v e ( > = t r a s ) b a n k p r e c h a r g e t i m e ( > = t r p ) r a s # c y c l e t i m e ( > = t r c ) a d d r e s s c o m m a n d c k
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 38 rev. 1. 0 june 2 013 figure 1 5 . posted cas# operation: al=2 read followed by a write to the same bank figure 1 6 . posted cas# operation : al=0 read followed by a write to the same bank c k # c m d a l = 2 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 4 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 5 > = t r c d [ a l = 2 a n d c l = 3 , r l = ( a l + c l ) = 5 , w l = ( r l - 1 ) = 4 , b l = 4 ] d q s d q c k d q s # c k # c m d a l = 0 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 2 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 3 > = t r c d [ a l = 0 a n d c l = 3 , r l = ( a l + c l ) = 3 , w l = ( r l - 1 ) = 2 , b l = 4 ] d q s d q c k d q s #
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 39 rev. 1. 0 june 2 013 figure 1 7 . data output (read) timing figure 18 . data input (write) timing c k # c k d q t d q s q m a x c k t c h t r p s t t r p r e d q s t c l d q s # d q s q q q t q h q t q h t d q s q m a x d q s # d q s # d q d q s t d q s h t w p r e d q s d m t d q s l t w p s l v i l ( a c ) v i h ( a c ) d d v i l ( d c ) v i h ( d c ) d d d m i n d m i n d q s # d m i n v i h ( a c ) v i l ( a c ) d m i n v i h ( d c ) v i l ( d c ) t d s t d s t d h t d h
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 40 rev. 1. 0 june 2 013 figure 1 9 . burst read operation : rl=5 (al=2, cl=3, bl=4) figure 20 . burst read operation : rl=3 (al=0 , cl=3 , bl =8) figure 2 1 . burst read followed by burst write : rl=5 , wl = ( rl - 1 ) = 4 , bl =4 c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t e d c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p n o p = < t d q s c k d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 a l = 2 c l = 3 r l = 5 d q s # c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 r e a d a n o p n o p n o p n o p n o p n o p n o p n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c l = 3 r l = 3 d q s # = < t d q s c k d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 c k c k # d q s c m d d q s t 0 t 1 t n - 1 t n t n + 1 t n + 2 t n + 3 t n + 4 t n + 5 p o s t c a s # r e a d a n o p n o p p o s t c a s # w r i t e a n o p n o p n o p n o p n o p d o u t a 0 r l = 5 d q s # t r t w ( r e a d t o w r i t e t u r n a r o u n d t i m e ) w l = r l - 1 = 4 d o u t a 1 d o u t a 2 d o u t a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 n o t e : t h e m i n i m u m t i m e f r o m t h e b u r s t r e a d c o m m a n d t o t h e b u r s t w r i t e c o m m a n d i s d e f i n e d b y a r e a d - t o - w r i t e - t u r n - a r o u n d - t i m e , w h i c h i s 4 c l o c k s i n c a s e o f b l = 4 o p e r a t i o n , 6 c l o c k s i n c a s e o f b l = 8 o p e r a t i o n .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 41 rev. 1. 0 june 2 013 figure 2 2 . seamless burst read operation : rl=5 , al= 2 , cl=3, bl=4 figure 2 3 . read burst interrupt timing: (cl=3, al=0, rl=3, bl=8) c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t c a s # r e a d a n o p p o s t c a s # r e a d b n o p n o p n o p n o p n o p n o p d o u t a 0 a l = 2 d q s # d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 c l = 3 r l = 5 n o t e : t h e s e a m l e s s b u r s t r e a d o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a r e a d c o m m a n d a t e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , a n d e v e r y 4 c l o c k f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d . c k # c k c m d r e a d a n o p r e a d b n o p n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : r e a d b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : r e a d b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r r e a d c o m m a n d . r e a d b u r s t i n t e r r u p t i o n b y w r i t e c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : r e a d b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s r e a d c o m m a n d . a n y o t h e r r e a d b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : r e a d b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r r e a d w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m r e a d t o p r e c h a r g e t i m i n g i s a l + b l / 2 w h e r e b l i s t h e b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r a n d n o t t h e a c t u a l b u r s t ( w h i c h i s s h o r t e r b e c a u s e o f i n t e r r u p t ) .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 42 rev. 1. 0 june 2 013 figure 2 4 . burst write operation : rl=5 (al=2 , cl=3) , wl=4, bl=4 figure 2 5 . burst write operation : rl=3 (al=0 , cl=3) , wl=2, bl=4 c k # c k t d q s s c m d c a s e 1 : w i t h t d q s s ( m a x ) > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t n p o s t e d c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e t d s s t d q s s t d s s c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # > = t w r w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # t d q s s t d s h t d q s s t d s h c a s e 2 : w i t h t d q s s ( m i n ) d q s d q s c k # c k < = t d q s s c m d > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t m t m + 1 t n w r i t e a n o p n o p n o p n o p n o p p r e c h a r g e n o p b a n k a a c t i v a t e c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 2 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # d q s > = t r p
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 43 rev. 1. 0 june 2 013 figure 26. burst write followed by burst read: rl=5 ( al=2, cl=3, wl=4, t wtr =2, b l =4 ) figure 27. seamless burst write operation rl=5 , wl=4 , b l =4 c k # c k c k e t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 2 t 3 n o p n o p n o p n o p p o s t c a s # r e a d a n o p n o p n o p n o p d q s a l = 2 d q s # w l = r l - 1 = 4 d q s # d q s c l = 3 r l = 5 > = t w t r d n a 0 d n a 1 d n a 2 d n a 3 d o u t a 0 d q n o t e : t h e m i n i m u m n u m b e r o f c l o c k f r o m t h e b u r s t w r i t e c o m m a n d t o t h e b u r s t r e a d c o m m a n d i s [ c l - 1 + b l / 2 + t w t r ] . t h i s t w t r i s n o t a w r i t e r e c o v e r y t i m e ( t w r ) b u t t h e t i m e r e q u i r e d t o t r a n s f e r t h e 4 b i t w r i t e d a t a f r o m t h e i n p u t b u f f e r i n t o s e n s e a m p l i f i e r s i n t h e a r r a y . t w t r i s d e f i n e d i n t h e t i m i n g p a r a m e t e r t a b l e o f t h i s s t a n d a r d . w r i t e t o r e a d = c l - 1 + b l / 2 + t w t r c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p p o s t c a s # w r i t e b n o p n o p n o p n o p n o p n o p d q s d q s # w l = r l - 1 = 4 d q s # d q s d n a 0 d n a 1 d n a 2 d n a 3 d q d n b 0 d n b 1 d n b 2 d n b 3 n o t e : t h e s e a m l e s s b u r s t w r i t e o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a w r i t e c o m m a n d e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , e v e r y f o u r c l o c k s f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 44 rev. 1. 0 june 2 013 figure 28. write bur st interrupt timing : (cl=3, al=0, rl=3, wl=2, bl=8) c k # c k c m d n o p w r i t e a n o p w r i t e b n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : w r i t e b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : w r i t e b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r w r i t e c o m m a n d . w r i t e b u r s t i n t e r r u p t i o n b y r e a d c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : w r i t e b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s w r i t e c o m m a n d . a n y o t h e r w r i t e b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : w r i t e b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r w r i t e w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m w r i t e t o p r e c h a r g e t i m i n g i s w l + b l / 2 + t w r w h e r e t w r s t a r t s w i t h t h e r i s i n g c l o c k a f t e r t h e u n i n t e r r u p t e d b u r s t e n d a n d n o t f r o m t h e e n d o f a c t u a l b u r s t e n d .
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 45 rev. 1. 0 june 2 013 figure 29. write data mask d q d q s d m d q s # t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h c k # c k c o m m a n d d q s d q s # d q w r i t e t w r w l t d q s s t d q s s d m c a s e 2 : m a x t d q s s d q s d q s # d q d m c a s e 1 : m i n t d q s s d a t a m a s k f u n c t i o n , w l = 3 , a l = 0 , b l = 4 s h o w n d a t a m a s k t i m i n g
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 46 rev. 1. 0 june 2 013 figure 30. burst read operation followed by precharge: (rl=4, al=1, cl=3 , bl=4, t rtp Q 2 clocks) figure 3 1 . burst read operation followed by precharge : (rl=4, al=1, cl=3, bl=8, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p p r e c h a r g e n o p n o p n o p b a n k a a c t i v e n o p d q s d q s # a l + b l ' / 2 c l k s d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q > = t r p a l = 1 c l = 3 r l = 4 > = t r a s > = t r t p c l = 3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p n o p d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 47 rev. 1. 0 june 2 013 figure 3 2 . burst read operation followed by precharge : (rl =5, al=2, cl=3, bl=4, t rtp Q 2 clocks) figure 3 3 . burst read operation followed by precharge : (rl=6, al=2, cl=4, bl=4, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 5 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 2 > = t r a s > = t r p c l = 3 > = t r t p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 6 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 4 a l = 2 > = t r a s > = t r p c l = 4 > = t r t p
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 48 rev. 1. 0 june 2 013 figure 3 4 . burst read operation followed by precha rge : (rl=4, al=0, cl=4, bl=8, t rtp >2 clocks) figure 3 5 . burst write operation followed by precharge : wl = ( rl - 1 ) = 3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + 2 + m a x ( t r t p , 2 t c k ) * c l = 4 a l = 0 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 > = t r p > = t r a s * : r o u n d e d t o n e x t i n t e g e r . c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 3 c o m p l e t i o n o f t h e b u r s t w r i t e
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 49 rev. 1. 0 june 2 013 figure 3 6 . burst write followed by precharge : wl = ( rl - 1 ) = 4 figure 3 7 . burst read operation with auto precharge : (rl=4,al=1, cl=3, bl=8, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 9 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 4 c o m p l e t i o n o f t h e b u r s t w r i t e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 a u t o p r e c h a r g e > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 > = t r p t r t p p r e c h a r g e b e g i n s h e r e f i r s t 4 - b i t p r e f e t c h p o s t c a s # r e a d a
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 50 rev. 1. 0 june 2 013 figure 3 8 . burst read operation with auto precharge : (rl=4, al=1, cl=3, bl=4, t rtp >2 clocks) figure 3 9 . burst read operation with auto precharge followed by activation to the same bank (t rc limit): rl=5(al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 a u t o p r e c h a r g e > = a l + t r t p + t r p a l = 1 r l = 4 t r t p t r p f i r s t 4 - b i t p r e f e t c h p r e c h a r g e b e g i n s h e r e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 51 rev. 1. 0 june 2 013 figure 4 0. burst read operation with auto precharge followed by an activation to the same bank (t rp limit): (rl=5 (al=2, cl=3, i nternal t rcd =3, bl=4, t rtp Q 2 clocks) figure 4 1. burst write with auto - precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t m t 2 t 3 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 2 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 52 rev. 1. 0 june 2 013 figure 42 . burst write with auto - precharge (wr+t rp ) : wl=4, w r=2, bl=4, t rp =3 figure 43 . refresh command c k # c k c m d t 0 t 3 t 6 t 7 t 8 t 9 t 1 2 t 4 t 5 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 4 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c c k # c k c k e t 0 t 1 t m t n t n + 1 t 2 t 3 p r e c h a r g e n o p n o p r e f r e f n o p a n y c m d h i g h > = t r p > = t r f c > = t r f c
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 53 rev. 1. 0 june 2 013 figure 44 . self refresh operation figure 45 . basic power down entry and exit timing diagr a m figure 46 . cke intensive environmen t c k # c k c k e t 0 t 1 t 5 t m t 2 t 3 c m d > = t x s n r t r p * t c h t c l t c k t 4 t 6 t n > = t x s r d t i s v i l ( a c ) v i h ( a c ) t i s n o p s e l f r e f r e s h o d t t a o f d t i s v i l ( a c ) t i h t i s t i h t i s t i h v i l ( d c ) v i l ( a c ) v i h ( a c ) v i h ( d c ) n o p n o p v a l i d n o t e 1 d e v i c e m u s t b e i n t h e " a l l b a n k s i d l e " s t a t e p r i o r t o e n t e r i n g s e l f r e f r e s h m o d e . n o t e 2 o d t m u s t b e t u r n e d o f f t a o f d b e f o r e e n t e r i n g s e l f r e f r e s h m o d e , a n d c a n b e t u r n e d o n a g a i n w h e n t x s r d t i m i n g i s s a t i s f i e d . n o t e 3 t x s r d i s a p p l i e d f o r r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . t x s n r i s a p p l i e d f o r a n y c o m m a n d e x c e p t a r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . c k # c k c o m m a n d c k e v a l i d t i h t c k e m i n t i h t i h t i h t i s t i s t i s n o p n o p n o p v a l i d v a l i d o r n o p t x p , t x a r d t x a r d s t c k e ( m i n ) e x i t p o w e r - d o w n m o d e d o n ' t c a r e e n t e r p o w e r - d o w n m o d e c k # c k e t c k e n o t e : d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d p r o p e r d l l o p e r a t i o n w i t h i n t e n s i v e c k e o p e r a t i o n c k t c k e t c k e t c k e
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 54 rev. 1. 0 june 2 013 figure 47 . cke intensive environment figure 48 . read to power - down entry c k # c k e t c k e n o t e : t h e p a t t e r n s h o w n a b o v e c a n r e p e a t o v e r a l o n g p e r i o d o f t i m e . w i t h t h i s p a t t e r n , d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d d l l o p e r a t i o n w i t h t e m p e r a t u r e a n d v o l t a g e d r i f t c k t c k e t c k e t c k e t x p t x p t r e f i r e f r e f c m d c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l r e a d o p e r a t i o n s t a r t s w i t h a r e a d c o m m a n d a n d d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 55 rev. 1. 0 june 2 013 figur e 4 9. read with autoprecharge to power - down entry figure 5 0. write to power - down entry c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d a q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q p r e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d p r e s t a r t i n t e r n a l p r e c h a r g e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t y t y + 1 t 1 t y + 2 t y + 3 w r q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r q w l d q s c k e c k d q s # q q q d q q q q q t w t r t i s t w t r
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 56 rev. 1. 0 june 2 013 figure 5 1. write with autoprecharge to power - down entry c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t x + 3 t x + 4 t 1 t x + 5 t x + 6 w r a q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r a q w l d q s c k e c k d q s # q q q d q q q q q w r * 1 t i s p r e w r * 1 p r e s t a r t i n t e r n a l p r e c h a r g e * 1 : w r i s p r o g r a m m e d t h r o u g h m r s
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 57 rev. 1. 0 june 2 013 figure 5 2 . refresh command to po w er - down entry figure 5 3 . active command to power - down entry figure 5 4. precharge / precharge - all command to power - down entry figure 5 5. mrs / emrs command to power - down entry c k # c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 r e f c k e c k t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a u t o - r e f r e s h c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 a c t c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a c t i v e c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 p r o r p r a c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a p r e c h a r g e o r p r e c h a r g e a l l c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 m r s o r e m r s c k e t i s t 1 1 t m r d
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 58 rev. 1. 0 june 2 013 figure 5 6 . asynchronous cke low event figure 5 7. clock frequency change in precharge power down mode c k # c k c k e t c k t d e l a y c k e a s y n c h r o n o u s l y d r o p s l o w c l o c k s c a n b e t u r n e d o f f a f t e r t h i s p o i n t t i s s t a b l e c l o c k s c k # c m d t 0 t 2 t 4 t x t x + 1 t y t y + 1 t y + 2 t y + 3 t y + 4 t 1 t z f r e q u e n c y c h a n g e o c c u r s h e r e t r p c k e o d t c k n o p n o p n o p n o p d l l r e s e t n o p v a l i d 2 0 0 c l o c k s t a o f d m i n i m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t t x p t i s t i s t i h o d t i s o f f d u r i n g d l l r e s e t
as4c 128 m 8 d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 59 rev. 1. 0 june 2 013 figur e 5 8. 60 - ball fbga package outline drawing information symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.010 -- 0.016 0.25 -- 0.40 d 0.311 0.315 0.319 7.90 8.00 8.10 e 0.3 40 0.394 0.0.398 9.90 10.00 10.10 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.315 -- -- 8.00 -- f -- 0.126 -- -- 3.20 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 d2 -- -- 0.081 -- -- 2.05 pin a1 index detail : "a" top view bottom view side view

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